A 58mW 1.2mm² HSDPA Turbo Decoder ASIC in 0.13µm CMOS

📋 论文概要

本文提出了一款用于HSDPA的turbo解码器ASIC，采用0.13µm CMOS工艺，实现了58mW功耗和1.2mm²面积。通过架构和算法优化，在满足3GPP R6标准的同时显著降低了功耗和成本。

💡 主要创新点

• 针对HSDPA应用，提出低功耗、小面积的turbo解码器ASIC架构，优化了关键模块的功耗。
• 可能采用了改进的迭代停止准则或存储器优化技术来降低面积和功耗。

🏷 关键词

📄 原文摘要

provide a compelling user experience has made HSPA an indispensable catalyst for a substantial subscriber transition from 2G to 3G [1]. Data rates reaching the full potential of 3GPP R6 from cost-effective mobile terminals with competitive power consumption are more crucial than ever for the commercial success of 3G and future of cellular data communications. The computational intensity of some of the critical functional blocks such as the demodulator and turbo decoder has made today’s HSDPA receivers power hungry and costly even at only 3.6Mb/s peak rate. This work explores the improvement potential for the turbo decoder from a design perspective, in a similar thrust to our recent work on HSDPA receiver [2]. Turbo decoding requires recursive computations that virtually preclude pipelined realizations, which makes high throu

👥 作者与机构

Christian Benkeser1, Andreas Burg1, Teo Cupaiuolo1, Qiuting Huang1,2, 1

ETH Zurich, Zurich, Switzerland Advanced Circuit Pursuit (ACP), Zollikon, Switzerland 2 Three years into the global deployment of 3G cellular services, the need to