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本文针对Gb/s级DRAM接口中供电电压变化和不同端接条件导致的信号完整性问题，提出了一种多转换率输出驱动器和优化的阻抗校准电路。该设计基于66nm CMOS工艺，实现了3.0Gb/s/pin的数据速率，有效提高了接口的鲁棒性。
Young Kyoung Choi, Jung Woo Lee, Seung Wook Kwack, Hyeong Ouk Lee, Won Joo Yun, Sang Hoon Shin, Kwan Weon Kim, Young Jung Choi, Ye Seok Yang Hynix Semiconductor, Icheon, Korea After the development of graphics DRAM interface based on ondie termination (ODT) standards, the speed of DRAM has greatly increased. However, the Gb/s interface has many overheads, for instance, the various supply voltage and the different termination conditions. In this work, a multi-slew-rate output driver is developed to cope with the supply voltage variation and the different I/O component capacitance (denoted by CIO) condition. For accurate data transfer, it is necessary to reduce the design loss in the impedance-calibration circuit and to minimize CIO in the coded output driver. We describe the circuits and methods that manage these issues. The reduction of simultaneous-switching output (SSO) noise is important in graphics DRAM with 32-bit single-ended I/Os. High
Dong Uk Lee, Shin Deok Kang, Nak Kyu Park, Hyun Woo Lee,