A 65nm Sub-Vt Microcontroller with Integrated SRAM and Switched-Capacitor DC-DC Converter 256 to improve speed and read reliability; devices in the readbuffer are lengthened to achieve higher speed and lower read current variability in sub-Vt.

📋 论文概要

该论文提出了一款65nm工艺下的亚阈值微控制器，集成了SRAM和开关电容DC-DC转换器。为了解决亚阈值区域延迟变化大、时序路径方差不同以及寄存器时序分布难以建模的问题，开发了定制时序闭合方法，通过商用工具生成路径列表并用定制脚本选择关键路径。

💡 主要创新点

• 提出针对亚阈值区域延迟变化大、不同时序路径方差差异大的定制时序闭合方法。
• 集成开关电容DC-DC转换器以优化电源效率，支持亚阈值操作。
• 在65nm工艺下实现微控制器与SRAM的完整亚阈值系统集成。

🏷 关键词

📄 原文摘要

Korbinian Huber2, Hans Moormann2, Anantha Chandrakasan1 A custom timing closure approach was developed to account for increased delay variability in sub-Vt. As shown in Fig. 16.7.3, delay distributions of timing paths in the microcontroller can have similar means but drastically different variances. Furthermore, setup and hold time distributions of various register types are not wellmodeled by canonical forms. To address these issues while keeping simulation times reasonable, a custom script was applied to an exhaustive list of timing paths generated by commercial software, in order to select a subset of paths for detailed analysis. The paths are first binned by nominal hold time margin. Within each bin, the script then estimates the delay variation (σ/μ) of each path, considering both device sizes and logic depth. Finally, paths with the highest σ/μ from each bin undergo Monte Carlo simulation, which

👥 作者与机构

Joyce Kwong1, Yogesh Ramadass1, Naveen Verma1, Markus Koesler2,