A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management

📋 论文概要

该论文介绍了一款在45nm SOI工艺下实现的SRAM宏单元，访问时间为450ps，采用两级体接触传感方案和动态功耗管理技术，分别实现了58%的读功耗降低和37%的漏电功耗降低。

💡 主要创新点

• 提出两级体接触传感方案，在恒定电压和频率下将读功耗降低58%
• 采用单器件动态泄漏抑制方案，无需唤醒周期即可将总漏电功耗降低37%

🏷 关键词

📄 原文摘要

45nm SOI technology [1]. The macro is adapted for use as the principal growable embedded-SRAM block in a 45nm ASIC library. We describe a two-stage, body-contacted sensing scheme that, among other improvements, achieves a 58% reduction in read power consumption under constant voltage and frequency compared to the previous generation macro [2]. Also described is a single-device dynamic-leakage-suppression scheme that reduces total leakage power consumption by 37% with no wake-up-cycle requirements. Figure 21.2.1 shows the SRAM macro features. SOI technology is typically exploited for high-performance processor applications [3]. To achieve the high performance, SRAM designs in SOI diverge from standard bulk offerings by eliminating sense amplifiers (SA) and limiting the number of cells on a bitline (BL) [3]. SOI technology is not limited to these high-e

👥 作者与机构

Harold Pilo1, Vinod Ramadurai1, Geordie Braceras1, John Gabric1,

Steve Lamphier1, Yue Tan2 1 IBM, Essex Junction, VT, 2IBM, Hopewell Junction, NY A 450ps access-time 512Kb SRAM macro is fabricated in a