An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane

📋 论文概要

本文提出了一种90nm CMOS 8Gb/s收发器，采用3倍过采样2阈值眼跟踪CDR电路，结合发送端5抽头FFE、接收端模拟均衡器和2抽头DFE，在-36.8dB损耗的160cm背板上实现了低于10^-12的误码率。

💡 主要创新点

• 提出3倍过采样2阈值眼跟踪CDR电路，提高时钟恢复精度和抖动容限。
• 集成5抽头FFE、模拟均衡器和2抽头DFE，有效补偿背板信道损耗。
• 在低成本背板上实现-36.8dB高损耗下的可靠数据传输。

🏷 关键词

📄 原文摘要

T. Takemoto1, T. Saito1, N. Chujo2, K. Yamamoto2, H. Kanai2, A. Hayashi1 1 Hitachi, Tokyo, Japan, 2Hitachi, Kanagawa, Japan IT systems such as servers and routers need high-speed lowerpower area-efficient chip-to-chip interconnections through backplane boards. These interconnections must overcome signal degradation due to the large insertion loss of low-cost boards. In this work, a 90nm CMOS 8Gb/s transceiver is developed. A TX 5tap FFE, an RX analog equalizer, and a 2-tap DFE combined with a 2-threshold eye-tracking CDR achieve a BER of less than 10-12 through a 160cm backplane board with -36.8dB loss at 4GHz and a transceiver power consumption of 232mW (transmission efficiency of 1.2Gb/s×dB/mW). A block diagram of the half-rate transmitter with a 5-tap FFE is shown in Fig. 5.1.1. A 5b data stream from a shift register is inverted every other bit and fed into output drivers that consist of 25 CMOS inverters in parallel. FFE tap coefficients are

👥 作者与机构

K. Fukuda1, H. Yamashita1, F. Yuki1, M. Yagyu1, R. Nemoto1,