TILE64TM Processor: A 64-Core SoC with Mesh Interconnect

📋 论文概要

该论文介绍了TILE64™处理器，一种具有64个核心的片上系统，通过网格互连解决传统单核和共享总线架构的扩展性问题，满足嵌入式应用的高性能需求。

💡 主要创新点

• 采用64个核心的网格互连架构，实现高效并行处理。
• 将处理器设计为面向嵌入式应用的片上系统，集成多种功能模块。

🏷 关键词

📄 原文摘要

Vince Leung, John MacKay, Mike Reif, Liewei Bao, John Brown, Matthew Mattina, Chyi-Chang Miao, Carl Ramey, David Wentzlaff, Walker Anderson, Ethan Berger, Nat Fairbanks, Durlov Khan, Froilan Montenegro, Jay Stickney, John Zook Tilera, Westborough, MA Centralized monolithic processor designs, such as single core and shared bus structures, are not scaling, leading to multicore designs becoming the norm [1-3]. Research highlights the benefits of mesh networks connecting these cores. [4,5]. The TILE64™ processor [6] is a multicore SoC targeting the high-performance demands of a wide range of embedded applications across networking and digital multimedia applications. Figure 4.4.1 shows a block diagram with 64 tile processors arranged in an 8×8 array. These tiles connect through a scalable 2D mesh network with high-speed I/Os on the periphery. Each general-purpose processor is identical and capable of running SMP Linux. Chip peak memory bandwidth is over 25GB/s using four 72-bit 800MHz DDR2

👥 作者与机构

Shane Bell, Bruce Edwards, John Amann, Rich Conlin, Kevin Joyce,