2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process

📋 论文概要

该论文在65nm逻辑工艺中实现了一个2Mb的2T增益单元存储器宏，工作频率2GHz，带宽128GB/s，解决了嵌入式存储器在逻辑工艺中兼顾高密度与高速的问题。

💡 主要创新点

• 采用2T增益单元替代传统SRAM，在逻辑工艺中实现更高存储密度。
• 实现2GHz操作频率与128GB/s带宽，达到2ns的快速周期时间，适用于标签RAM等读密集型应用。

🏷 关键词

📄 原文摘要

Muhammad Khellah, Jason Howard, Greg Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi Intel, Hilsboro, OR As silicon technology scales, the possibility of fabricating dense memories [1-4] is of great interest, particularly if the solution has low to no additional process cost. We demonstrate a 2Mb 2T gaincell macro with 128GB/s bandwidth, fast 2ns cycle time, operating at 2GHz in a native 65nm logic process. Fast read access and cycle times are critical in lookup applications such as tag RAMs in microprocessors where read queries are abundant. In such a scenario replacing SRAM with a denser fast memory is desired. The 2T fully pipelined gain-cell macro features non-destructive read, partial-write support and sustains 8-cycle successive access to the same memory bank. The macro is fabricated in a high-performance 65nm process [5] featuring 1.2nm nitrided gate oxide, 35nm gate length, enhanced channel strain, NiSi silicide, 8 layers of Cu metal interconnect, and low-κ ILD

👥 作者与机构

Dinesh Somasekhar, Yibin Ye, Paolo Aseron, Shih-Lien Lu,