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该论文提出了一种基于局部无源插值的高分辨率时间-数字转换器(TDC),在90nm CMOS工艺下实现了4.7ps分辨率、0.7-LSB单次精度和19pJ/转换的低功耗。解决了传统Vernier TDC延迟线过长的问题,适用于时间飞行测量、抖动测试等应用。
Infineon Technologies, Munich, Germany Technical University Munich, Munich, Germany 2 Time-to-digital converters (TDC) support the industry wide trend of replacing mixed-signal functionality by digital realizations. High-resolution TDCs [1] become increasingly popular for time-offlight measurements, full-speed testing, e.g., jitter measurement, clock and data recovery, measurement and instrumentation, and digital PLLs. As the speed leverage of technology scaling decreases below 100nm, robust TDCs with sub-gate-delay resolution are essential. The Vernier TDC [2] requires long delay lines, thus suffers from large latency, area and power consumption. Latency and a resolution limited by the inherent variation-related pulse-width modification are the drawbacks of the pulse-shrinking approach
Stephan Henzler1, Siegmar Koeppe1, Winfried Kamp1, Hans Mulatz2, Doris Schmitt-Landsiedel2