A 10Gb/s IEEE 802.3an-Compliant Ethernet Transceiver for 100m UTP Cable in 0.13µm CMOS stringent specification of >60dB linearity over the frequency band of 1 to 400MHz on the combined output of TXDAC, ECDAC and the subtraction circuit within the PGA.

📋 论文概要

该论文提出了一款符合IEEE 802.3an标准的10Gb/s以太网收发器，采用0.13µm CMOS工艺，可实现100米UTP电缆传输。重点介绍了发送器和EC DAC的分段电流舵架构，通过6位温度计编码改善DNL和减小非线性毛刺能量。

💡 主要创新点

• 采用分段电流舵架构，6位MSB温度计编码，显著改善DNL至低于0.5LSB并减小非线性毛刺能量。
• 电流源精度基于INL良率3σ要求进行设计，并采用双公共质心布局提高匹配性。

🏷 关键词

📄 原文摘要

Vishnu Balan, Michael Inerfield, Dariush Dabiri, John Dring, Sachin Goel, Kumaraguru Muthukumaraswamy, Frank McCarthy, Glenn Golden, Jiangfeng Wu, Susan Arno, Sanjay Kasturia The architecture for both the TX and EC DAC is chosen to be segmented current steering. 6 MSBs are thermometer encoded to achieve significantly better than 0.5LSB DNL, and reduced nonlinear glitch energy. The accuracy of the current sources is based on the INL yield specification of 3σ. This is calculated on the basis of the formula presented in [3]. The layout of this currentsource array (CSA) is done with a double common-centroid scheme [3]. CML latches with CML buffers drive the main current cells, and are designed to minimize the large transient current spikes, charge injection, and the glitches at the currentsource drains. One of the unit cells of the DAC with the current cell driven by such latches is shown in Fig. 5.5.3. The DAC output current is provided by a transformer center tap as shown in

👥 作者与机构

Sandeep Gupta, Jose Tellado, Sridhar Begur, Frank Yang,