A 10.3125Gb/s Burst-Mode CDR Circuit using a ΔΣ DAC

📋 论文概要

该论文提出了一种10.3125Gb/s的突发模式时钟数据恢复(CDR)电路，采用单个门控压控振荡器(GVCO)和ΔΣ数模转换器(DAC)架构，解决了传统突发模式CDR在快速锁定、长连续相同码(CID)容限和高抖动容限之间的权衡问题。实现了1位瞬时锁定、160位CID容限和0.27UIpp抖动容限。

💡 主要创新点

• 首次将ΔΣ DAC应用于GVCO-based突发模式CDR中，通过数字控制GVCO频率实现快速相位锁定和长CID容限。
• 采用单个GVCO的简单架构，避免了传统多相时钟或锁相环的复杂设计，降低了功耗和面积。
• 通过ΔΣ调制抑制了GVCO的电压-频率非线性，提高了抖动性能。

🏷 关键词

📄 原文摘要

transmission that has an instantaneous response, tolerance to long consecutive-identical digits (CIDs), and high jitter tolerance. In this paper, a burst-mode CDR circuit achieves instantaneous locking of 1b, CID tolerance of 160b, and jitter tolerance of 0.27UIpp at 10.3125Gb/s operation. These characteristics are provided by a CDR architecture using a single gated VCO (GVCO) and a ΔΣ DAC. The simple architecture of the GVCO-based bust-mode CDR circuit provides instantaneous phase locking, which reduces the overhead time and increases the transmission efficiency. Conventional GVCO-based CDR circuits [1-3] use two or more GVCOs. The multiple-GVCO architecture suffers from frequency difference between GVCOs. A main GVCO aligns the phase of the

👥 作者与机构

Jun Terada1, Kazuyoshi Nishimura1, Shunji Kimura2,

Hiroaki Katsurai1, Naoto Yoshimoto2, Yusuke Ohtomo1 1 NTT, Atsugi, Japan, 2NTT Chiba, Japan PONs such as 10G-EPON systems require a burst-mode CDR circuit for upstream