A Noise-Coupled Time-Interleaved ΔΣ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR

📋 论文概要

该论文提出了一种基于噪声耦合和时间交错技术的ΔΣ ADC，在4.2MHz带宽内实现了-98dB THD和79dB SNDR，解决了宽带高分辨率ADC的功耗效率问题。通过噪声耦合增强噪声整形效果，时间交错提高采样率，实现了低功耗高性能。

💡 主要创新点

• 提出了噪声耦合结构，在不增加阶数的情况下增强噪声整形效果，降低带内噪声。
• 结合时间交错技术，有效提高整体采样速率，同时保持高分辨率。
• 采用开关电容电路实现，功耗低于同类设计，FOM优异。

🏷 关键词

📄 原文摘要

Kaoru Takasuka2, Seiji Takeuchi2, Gabor C. Temes1 1 Oregon State University, Corvallis, OR, 2Asahi Kasei, Atsugi, Japan Wideband high-resolution ΔΣ ADCs with low power consumption are needed in many wired and wireless communication (as well as consumer) applications. There has been continued effort to design efficient modulator structures that meet these requirements. Recently, several discrete-time ΔΣ ADCs have been reported with signal BWs in the MHz range and FOMs below 0.5pJ/conversionstep [1,2]. Discrete-time ΔΣ ADCs based on SC circuitry have several advantages over their continuous-time counterparts: 1. the performance is scalable with clock frequency and is less sensitive to clock jitter; 2. the accuracy relies on good capacitor matching, which is relatively easy to achieve; 3. there are well-established design methodologies available. The disadvantages are increased power requirements for the same speed, and a need for an

👥 作者与机构

Kyehyung Lee1, Jeongseok Chae1, Mitsuru Aniya2, Koichi Hamashita2,