A 150MS/s 133µW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous BinarySearch sub-ADC

📋 论文概要

该论文提出了一种采用比较器异步二进制搜索子ADC的两步7位ADC，在90nm数字CMOS工艺下实现了150MS/s的采样率，功耗仅133µW，解决了中高速、中低分辨率ADC能效提升的问题。

💡 主要创新点

• 提出比较器异步二进制搜索（CABS）架构，通过异步比较器链实现快速逐次逼近，无需传统SAR逻辑和时钟控制，显著降低功耗。
• 采用两步转换结构，先进行1位粗比较和D/A转换，再进行6位CABS细转换，在保持高速的同时优化了能效。

🏷 关键词

📄 原文摘要

in medium- to high-speed (10s of MS/s to a few GS/s) and medium- to low-resolution (4b to 9b) A/D converters. Current state-of-the-art FOM is 65fJ [1]. These efficiency improvements are primarily driven by mobile, wireless applications and sensor networks. In this paper, a 2-step 7b ADC consists of a T/H, followed by a 1b comparison and D/A conversion, and a 6b comparator-based asynchronous binary-search (CABS) conversion (Fig. 12.3.1). The 7b ADC operates as follows: the passive T/H samples the input signal on a capacitance, the 1b comparator determines the sign of the input (MSB, B[6]) and steers a capacitive DAC. The DAC subtracts ¼ of the full-scale range in charge from one of the input nodes, changing simultaneously differential signal and common-mode level to be in range of the 6b CABS converter.

👥 作者与机构

Geert Van der Plas1, Bob Verbruggen1,2, 1

IMEC, Leuven, Belgium, 2Vrije Universiteit Brussel, Brussels, Belgium In recent years, significant progress is made in lowering the power consumption