A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-κ Metal Gate CMOS

📋 论文概要

该论文介绍了一款专为移动互联网设备和超移动PC设计的低功耗IA处理器，采用45nm Hi-κ金属栅极CMOS工艺，功耗范围在1W到2W之间。通过in-order双发射双线程流水线、独立整数/浮点执行单元以及优化的缓存架构，实现了与主流UMPC相当的性能，同时显著降低了平均功耗。

💡 主要创新点

• 采用45nm Hi-κ金属栅极CMOS工艺实现低功耗与高性能的平衡，支持Sub-1W到2W的动态功耗范围。
• 设计了一个in-order双发射双线程流水线，结合32KB指令和24KB数据L1缓存以及512KB L2缓存，优化了能效比。
• 集成了独立整数和浮点执行单元以及x86前端，支持533MT/s双模前端总线，适应移动设备的多样化需求。

🏷 关键词

📄 原文摘要

specifically designed for Mobile Internet Devices (MID) and UltraMobile PCs (UMPC) where average power consumed is in the order of a few hundred mW (as measured by MobileMark’05 OP @ 60 nits brightness) with performance similar to mainstream Ultra-Mobile PCs. The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32KB instruction and 24KB data L1 caches, independent integer and floating point execution units, ×86 front end execution unit, a 512KB L2 cache and a 533 MT/s dual-mode (GTL and CMOS) front-side-bus (FSB); a block diagram is shown in Fig. 13.1.1. The design contains 47M transistors in a die size under 25mm2 manufactured in a 9-metal 45nm CMOS process with optimized transistors for low leakage [1] packaged in a

👥 作者与机构

Gianfranco Gerosa, Steve Curtis, Mike D’Addeo, Bo Jiang,

Belliappa Kuttanna, Feroze Merchant, Binta Patel, Mohammed Taufique, Haytham Samarchi Intel, Austin, TX This paper describes a low-power Intel® Architecture (IA) processor