⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种采用脉冲宽度和脉冲位置调制的65nm CMOS类E功率放大器，实现了28.6dBm的输出功率，解决了近瓦级输出功率在纳米CMOS工艺中因电源电压缩放和低阻抗匹配带来的挑战。
near-watt-level output power in nanometer CMOS is difficult to satisfy owing to the power supply voltage scaling with minimum feature size. High performance is problematic because most PA interfaces are defined by a 50Ω characteristic impedance whereas the optimum termination for a near-watt level output is around 1 to 5Ω. A large output power is usually obtained using either a passive matching network, or a power combiner with multiple PAs [1]. A significant loss is incurred in either network. Switching amplifiers exploit the ever improving switching performance of CMOS transistors to provide high power output and the simplicity of the output network to attain good power efficiency. However, because switching PAs are nonlinear with respect to input amplitude, they cannot, under normal driving conditions, amplify a modulated signal with a n
Jeffrey Walling1,2, Hasnain Lakdawala2, Yorgos Palaskas2,
Ashoke Ravi2, Ofir Degani2, Krishnamurthy Soumyanath2, David Allstot1 1 University of Washington, Seattle, WA Intel, Hillsboro, OR 2 The desire for