An 8×3.2Gb/s Parallel Receiver with Collaborative Timing Recovery

📋 论文概要

本文提出一种8通道3.2Gb/s并行接收器，采用协作时序恢复技术，利用单个全局时序恢复模块替代每通道独立的时钟恢复，从而降低功耗。通过收集所有通道的定时误差信息进行协作恢复，适用于同步并行数据链路。

💡 主要创新点

• 使用单一全局时序恢复代替每通道时钟恢复，显著降低功耗
• 收集所有通道的定时误差信息进行协作时序恢复，提高恢复精度
• 适用于同步并行高速数据接口（如FBDIMM）

🏷 关键词

📄 原文摘要

high-performance computing systems that enable high-throughput CPUto-CPU and CPU-to-memory data transfers. Slower wide-bus interfaces have been replaced by a narrower collection of higherspeed serial links (e.g., FBDIMM [1]) to save valuable pin resources. This paper explores the architecture and design of an 8×3.2Gb/s parallel receiver that relies on collaborative timing recovery. Given synchrony between parallel data channels, perchannel clock recovery can be replaced by a single global timingrecovery (TR) block to save power. Moreover, collecting timingerror information across all of the data channels greatly enhances effective edge transition density, which decreases dithering jitter on the recovered clock. Figure 25.9.1 presents an overview of the experimental setup and

👥 作者与机构

Ankur Agrawal1, Pavan Kumar Hanumolu2, Gu-Yeon Wei1, 1

Harvard University, Cambridge, MA Oregon State University, Corvallis, OR 2 High-speed parallel transceivers are an integral part of