A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-κ Metal-Gate CMOS Technology

📋 论文概要

本文提出一种153Mb SRAM设计，采用动态正向体偏置技术增强存储单元的稳定性，并降低泄漏功耗。该设计基于45nm高κ金属栅CMOS工艺，解决了在器件变异增大和泄漏电流上升情况下的低电压操作稳定性问题。

💡 主要创新点

• 提出完全集成的动态正向体偏置方案，在读写操作中动态调整体偏置以提升稳定性裕度。
• 通过动态体偏置和工艺优化实现泄漏电流的大幅降低，同时保持高密度存储阵列。

🏷 关键词

📄 原文摘要

drive the increase of on-die memory density to meet performance needs in various applications such as microprocessors. Meanwhile, the device variation and leakage are increasing as the miniaturization of the transistor continues. As a result, it is increasingly challenging to develop SRAM with adequate stability margin for low-voltage operation while keeping the power consumption low enough to meet system-level power requirements. We report a 153Mb SRAM design that is optimized for a 45nm high-κ metal-gate technology [1]. The design contains fully integrated dynamic forward-body-bias to achieve lower voltage operation while keeping low the area and power overhead. The dynamic sleep design, which was developed at the

👥 作者与机构

Fatih Hamzaoglu1, Kevin Zhang1, Yih Wang1, Hong Jo Ahn1,

Uddalak Bhattacharya1, Zhanping Chen1, Yong-Gee Ng1, Andrei Pavlov1, Ken Smits2, Mark Bohr1 1 Intel, Hillsboro, OR , 2Intel, Santa Clara, CA CMOS technology scaling continues to