A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering

📋 论文概要

该论文提出了一种基于低过采样率ΔΣ调制和嵌入式FIR噪声滤波的1GHz分数N PLL时钟发生器。解决了宽带PLL中环形VCO无法有效抑制高频量化噪声的问题，实现了小于1ppm的频率分辨率并兼顾短期与长期抖动性能。

💡 主要创新点

• 提出低过采样率（Low-OSR）ΔΣ调制技术，降低量化噪声在带内的贡献，避免宽带PLL设计中噪声恶化。
• 采用嵌入式FIR噪声滤波结构，在不增加额外模拟滤波器的情况下增强高频量化噪声抑制能力。
• 实现1GHz工作频率，同时满足数字时钟系统对短期和长期抖动的严格要求。

🏷 关键词

📄 原文摘要

Offering less than 1ppm frequency resolution, a ΔΣ fractional-N PLL enables flexible frequency planning and reliable spread spectrum modulation for digital clock generation [1, 2]. Use of low-cost ring VCOs however, mandates a wideband PLL design, which makes it difficult for the PLL to filter out high-frequency quantization noise from the ΔΣ modulator. In many digital clocking systems, such as serial links and microprocessors, short-term jitter is as important as long-term jitter. Hence, when high-frequency quantization noise is not sufficiently suppressed by the PLL it can easily degrade the overall system performance. This paper describes a noise filtering method for quantization noise reduction that is not sensitive to PVT variations. The resulting fractional-N PLL clock generator is the first one demonstrated with an oversampling ratio (OSR) of about 10, where the OSR is defined by fref/(2fbw) in this work.

👥 作者与机构

Xueyi Yu, Yuanfeng Sun, Li Zhang, Woogeun Rhee, Zhihua Wang

Tsinghua University, Beijing, China