A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS

📋 论文概要

该论文提出了一种在65nm CMOS工艺下、1V供电、11位200MS/s的流水线ADC，采用数字后台校准技术来解决低电压下高增益运放设计困难的问题。通过校准技术，有效克服了先进纳米工艺中增益不足和电容失配的限制。

💡 主要创新点

• 采用数字后台校准技术，无需中断正常转换即可校正增益误差和电容失配。
• 在65nm低电压CMOS工艺下实现了11位200MS/s的高性能流水线ADC。

🏷 关键词

📄 原文摘要

demand high-resolution high-speed low-voltage ADCs. Pipelined ADCs are well suited for these applications. However, traditional designs of such high-resolution ADCs rely on high-gain operational amplifiers along with good capacitor matching, to deliver the required performance. One key limitation of this approach is that designing a high-gain amplifier is becoming more and more difficult in advanced nanometer technologies, i.e., 65nm, especially at low supply voltages. To overcome this problem, background calibration had been applied to pipelined ADCs, which resolves the gain problem by moving the design challenges from the analog to the digital domain. The cost of digital calibration is decreasing rapidly as the digital circuitry occupies smaller area as technology advances. This paper

👥 作者与机构

Kang-Wei Hsueh, Yu-Kai Chou, Yu-Hsuan Tu, Yi-Fu Chen,

Ya-Lun Yang, Hung-Sung Li MediaTek, Hsin-Chu, Taiwan High-definition video system and communication equipments in deep-submicron