Implementation of a Third-Generation 16-Core 32Thread Chip-Multithreading SPARC® Processor

📋 论文概要

本文介绍了第三代16核32线程SPARC处理器的物理实现，该处理器针对高性能服务器优化，兼顾单线程与多线程应用。通过内存阵列、寄存器文件和浮点硬件的电路创新来提升性能。

💡 主要创新点

• 在内存阵列中采用创新的电路设计，提升读写速度和能效。
• 寄存器文件使用新型电路结构，降低延迟和功耗。
• 浮点硬件引入定制化电路，提高浮点运算性能。

🏷 关键词

📄 原文摘要

Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar Sun Microsystems, Santa Clara, CA This third-generation chip-multithreading (CMT) SPARC processor is targeted for high-performance servers, and is optimized for both single- and multi-threaded applications. The architecture highlights are provided in [1], while this paper focuses on the physical implementation aspects, providing an overview of circuit innovations in memory arrays, register files, and floating-point hardware that boost the performance and circuit robustness with low area overhead. The 396mm2 chip, shown in Fig. 4.2.1, is fabricated in a 11M 65nm CMOS process and operates at a nominal frequency of 2.3GHz, consuming a maximum power of 250W at 1.2V. Power-management techniques include clock gating at corecluster level and power throttling through a single-thread-issue

👥 作者与机构

Georgios Konstadinidis, Mamun Rashid, Peter F. Lai, Yukio Otaguro,