A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS

📋 论文概要

该论文提出了一种工作在90nm数字CMOS工艺下的5位1.75GS/s折叠闪存ADC，总功耗仅2.2mW。通过采用折叠技术有效减少了比较器数量，从而在保持高速性能的同时显著降低了功耗，适用于UWB等无线接收器中的高速低分辨率转换需求。

💡 主要创新点

• 采用折叠架构替代传统全闪存，大幅减少比较器数量，从而在90nm工艺下实现极低功耗（2.2mW）和高速（1.75GS/s）的折中。
• 结合折叠与闪存子转换器设计，优化了输入带宽和采样速率，并保持了5位分辨率所需的线性度。

🏷 关键词

📄 原文摘要

IMEC, Leuven, Belgium Vrije Universiteit Brussel, Brussel, Belgium 2 High-speed low-resolution ADCs are an essential part of receivers for wireless standards such as UWB. These converters have to combine the stringent speed specifications with the demand for low power consumption. Flash architectures are often chosen because they offer the largest speed. However, in this architecture, area and power depend exponentially on the resolution since the comparators are often the largest contributor to the overall power consumption. Folding is a well-known technique used to reduce the number of comparators in an ADC while maintaining high speed. It was previously implemented by generating a number of zero crossings with folding amplifiers, often in combination with interpolation or averaging [1, 2]. In this design, a folding factor of 2 is realized as in [3] but with only dynamic power consumption and without using

👥 作者与机构

Bob Verbruggen1,2, Jan Craninckx1, Maarten Kuijk2, Piet Wambacq1,2, Geert Van der Plas1