An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler

📋 论文概要

该论文提出了一款具有8640 MIPS性能的多核SoC，集成了8个CPU和8个RAM，通过独立电源关断控制实现功耗优化，并采用自动并行化编译器自动将串行程序转换为多核并行代码，解决了嵌入式应用中的能效与编程复杂度问题。

💡 主要创新点

• 集成8个CPU和8个RAM的多核SoC，峰值性能达8640 MIPS，适用于高性能嵌入式应用。
• 实现每核和每RAM的独立电源关断控制，动态管理功耗以提升能效。
• 开发自动并行化编译器，自动将串行程序转换为多核并行代码，降低多核编程门槛。

🏷 关键词

📄 原文摘要

Tomoichi Hayashi1, Osamu Nishii1, Yoshihiko Yasu1, Atsushi Hasegawa1, Masashi Takada2, Masaki Ito2, Hiroyuki Mizuno2, Kunio Uchiyama2, Toshihiko Odaka2, Jun Shirako3, Masayoshi Mase3, Keiji Kimura3, Hironori Kasahara3 1 Renesas Technology, Tokyo, Japan Hitachi, Tokyo, Japan 3 Waseda University, Tokyo, Japan 2 Power efficient SoC design for embedded applications requires several independent power-domains where the power of unused blocks can be turned off. An SoC for mobile phones [1] defines 23 hierarchical power domains but most of the power domains are assigned for peripheral IPs that mainly use low-leakage high-Vt transistors. Since high-performance multiprocessor SoCs use leaky low-Vt transistors for CPU sections, leakage power savings of these CPU sections is a primary objective. We develop an SoC with 8 processor cores and 8 user RAMs (1 per core) targeted for power-efficient high-performance embedded applications. We

👥 作者与机构

Masayuki Ito1, Toshihiro Hattori1, Yutaka Yoshida1, Kiyoshi Hayase1,