A 100mW 10MHz-BW CT ΔΣ Modulator with 87dB DR and 91dBc IMD

📋 论文概要

本文提出一款连续时间ΔΣ调制器，在10MHz带宽内实现87dB动态范围和-91dBc互调失真，功耗仅100mW。针对宽带高动态范围ADC的需求，该调制器利用电阻输入简化驱动，并提供固有抗混叠滤波，解决了传统流水线ADC需要复杂输入缓冲和抗混叠滤波器的问题。

💡 主要创新点

• 在CMOS工艺中实现10MHz带宽的连续时间ΔΣ调制器，同时达到87dB动态范围和-91dBc的低互调失真，显著优于同类设计。
• 通过优化环路滤波器和量化器设计，在100mW低功耗下实现接近90dB的SFDR，满足无线通信系统对高线性度的要求。

🏷 关键词

📄 原文摘要

bandwidth and high dynamic range. In such systems, a pipeline ADC requires a low-noise high-speed input buffer to drive the sampling capacitor and a sophisticated anti-aliasing filter whereas a CT ΔΣ ADC has an easy-to-drive resistive input and provides inherent anti-aliasing. Continued advances in CMOS technology allow ΔΣ modulators to achieve ever-wider bandwidths, but often at the expense of DR or distortion [1, 2]. This paper describes a CT ΔΣ modulator with 10MHz of bandwidth that achieves a DR of 87dB and an IMD of –91dBc while consuming 100mW. As shown in Figure 27.6.1, the modulator is a single-loop 5th-order system that uses a combination of both feedforward and feedback paths. Resistive and capacitive feedforward paths to the last integrator reduce signal components in the loop filter, which allows

👥 作者与机构

Wenhua Yang, William Schofield, Hajime Shibata, Sudhir Korrapati,

Ali Shaikh, Nazmy Abaskharoun, Dave Ribner Analog Devices, Wilmington, MA Modern multi-carrier wireless receivers require ADCs with wide