An 820µW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS

📋 论文概要

本文提出了一种在90nm数字CMOS工艺下实现的9位40MS/s噪声容忍动态SAR ADC，功耗仅为820µW。通过采用噪声容忍技术，有效解决了SAR ADC中比较器热噪声限制分辨率的问题，实现了高能效模数转换。

💡 主要创新点

• 提出噪声容忍技术以降低比较器热噪声对SAR ADC分辨率的限制。
• 采用动态电路设计实现低功耗高性能的SAR ADC。
• 在90nm数字CMOS工艺中实现了820µW超低功耗的9位40MS/s转换性能。

🏷 关键词

📄 原文摘要

battery-powered devices demand the adoption of cheap and power-efficient ADCs. SAR architectures have been recently demonstrated as able to achieve high power efficiency in the moderate-resolution/mediumbandwidth range [1]. However, when the comparator determines in first instance the overall performance, as in most SAR ADCs, comparator thermal noise can limit the maximum achievable resolution. More than 1 and 2 ENOB reductions are observed in [1] and [2], respectively, because of thermal noise, and degradations could be even worse with scaled supply voltages and the extensive use of dynamic regenerative latches without pre-amplification. Unlike mismatch, random noise cannot be compensated by calibration and would finally demand a quadratic increase in power consumption unless alternative circuit techniques are devised.

👥 作者与机构

Vito Giannini1, Pierluigi Nuzzo1, Vincenzo Chironi2,

Andrea Baschirotto2, Geert Van der Plas1, Jan Craninckx1 1 IMEC, Leuven, Belgium, 2University of Salento, Lecce, Italy Current trends in analog/mixed-signal design for