⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文设计并实现了一个全集成双二进制收发器，采用90nm CMOS工艺，数据速率达到20Gb/s。通过利用双二进制信令的带宽效率（频谱仅为NRZ的一半）以及信道固有滚降特性，有效克服了背板通信中的信道损耗问题。
The ever growing volume of backplane communications pushes the data rate toward 20Gb/s for the next-generation transceivers. Over the years, chip designers have been seeking different data formats to overcome the loss of electrical channels. Among the existing solutions, duobinary signaling manifests itself in bandwidth efficiency as (1) its spectrum occupies only half as wide as that of NRZ data; (2) it incorporates the intrinsic roll-off bandwidth of the channel as part of the desired response. The design and experimental verification of a fully-integrated duobinary transceiver in 90nm CMOS is described. The transceiver achieves 20Gb/s error-free transmission over a 40cm Rogers and a 10cm FR4 channels. Figure 5.3.1 shows the conceptual illustration of the transceiver. Since the duobinary signaling is defined as the sum of the present bit and the previous one, it possesses a transfer function of 1+z–1,
Jri Lee, Ming-Shuan Chen, Huai-De Wang
National Taiwan University, Taipei, Taiwan