A Clockless ADC/DSP/DAC System with ActivityDependent Power Dissipation and No Aliasing

📋 论文概要

该论文提出了一种无时钟的ADC/DSP/DAC系统，通过消除采样和时钟信号，实现了无混叠、无杂散频率且功耗随输入活动动态降低的特性，适用于助听器等便携实时应用。该系统是首个实现连续时间数字信号处理的尝试。

💡 主要创新点

• 提出无时钟架构，消除采样和时钟，避免了传统DSP中的混叠和时钟相关杂散频率。
• 实现活动相关功耗，输入活动减小时功耗自动降低，适合便携应用。
• 连续时间操作保留了极快的瞬态响应能力，可应用于功率电子等领域。

🏷 关键词

📄 原文摘要

The fixed sampling and clock rates in conventional DSPs result in power dissipation determined by the highest frequency to be processed. If sampling and clock are eliminated, one has a DSP operating in continuous-time [1], with no aliasing, no tones at frequencies not related to the input, and with a power dissipation that goes down as the input activity decreases, offering promise in the context of portable real-time applications (e.g., hearing aids). The absence of sampling also makes possible very fast transient performance in power electronics [2]. The only attempt so far to implement this approach on a custom-designed chip [3] resulted in very large area and power, and large inter-block interference made it impossible to operate the ADC at the same time with the rest of the system. In this work, these issues are addressed and solved, and an entire ADC/DSP/DAC 8b system is implemented in a UMC

👥 作者与机构

Bob Schell, Yannis Tsividis

Columbia University, New York, NY