A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

📋 论文概要

该论文提出了一个采用60nm工艺的6Gb/s/pin GDDR5图形DRAM，通过多方面的时钟技术和ISI/SSN降低技术解决高速信号完整性问题，实现了高数据速率传输。

💡 主要创新点

• 设计了包含转发时钟和数据训练的多方面时钟架构，支持6Gb/s高速I/O操作。
• 引入码间干扰(ISI)和同步开关噪声(SSN)降低技术，提升信号完整性。
• 在60nm CMOS工艺下实现单端信令的6Gb/s/pin速率，满足高性能图形DRAM需求。

🏷 关键词

📄 原文摘要

Dae-Hyun Chung, Jin-Gook Kim, Si-Hong Kim, Min-Sang Park, Jae-Hyung Lee, Sam-Young Bang, Ho-Kyung Lee, In-Soo Park, Jae-Sung Kim, Dae-Hyun Kim, Hye-Ran Kim, Yong-Jae Shin, Cheol-Goo Park, Gil-Shin Moon, Ki-Woong Yeom, Kang-Young Kim, Jae-Young Lee, Hyang-Ja Yang, Seong-Jin Jang, Joo Sun Choi, Young-Hyun Jun, Kinam Kim Samsung Electronics, Hwasung, Korea Demand for high-speed DRAM in graphics application pushes a single-ended I/O signaling to operate up to 6Gb/s [1]. To maintain the speed increase, the GDDR5 specification shifts from GDDR3/4 with respect to forwarded clocking, data training for write and read de-skewing, clock training, channel-error detection, bank group and data coding. This work tackles challenges in GDDR5 such as clock jitter and signal integrity. Figure 14.5.1 is an implemented block diagram of GDDR5 I/O interface. It consists of data transceivers including decision feedback equalizer

👥 作者与机构

Seung-Jun Bae, Young-Soo Sohn, Kwang-Il Park, Kyoung-Ho Kim,