A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

📋 论文概要

该论文提出了一种用于DRAM的全数字延迟锁定环（DLL），工作频率范围为0.1至1.5GHz，功耗仅为4.2mW。它通过双占空比校正电路和更新齿轮电路解决了传统数字DLL在宽频率范围内抖动大、功耗高和占空比校正能力不足的问题。

💡 主要创新点

• 提出双占空比校正电路，能够在宽频率范围内有效校正时钟占空比。
• 引入更新齿轮电路，优化了DLL的锁定时间和抖动性能，降低了功耗。

🏷 关键词

📄 原文摘要

Ji Yeon Yang, Hyeng Ouk Lee, Dong Uk Lee, Sujeong Sim, Young Ju Kim, Won Jun Choi, Keun Soo Song, Sang Hoon Shin, Hyang Hwa Choi, Hyung Wook Moon, Seung Wook Kwack, Jung Woo Lee, Young Kyoung Choi, Nak Kyu Park, Kwan Weon Kim, Young Jung Choi, Jin-Hong Ahn, Ye Seok Yang Hynix Semiconductor, Icheon, Korea Digital DLLs are widely used for de-skewing external clocks and driver output clocks in memory applications. The DLL needs to have low jitter, low power consumption, and duty-cycle-correction (DCC) capability over a wide frequency range. The conventional digital DLL has a dual loop and a phase-blending mixer for DCC operation [1-5]. Even though the conventional DLL can be augmented by an improved digital mixer [2], it is difficult to obtain high-precision precise DCC without a duty-cycle-error detector. We design a DLL that has a slew-rate controlled DCC with a fully digital controlled duty-cycle-error detector and has the update

👥 作者与机构

Won-Joo Yun, Hyun Woo Lee, Dongsuk Shin, Shin Deok Kang,