Circuit Design for Voltage Scaling and SER Immunity on a Quad-Core Itanium® Processor

📋 论文概要

该论文针对四核安腾处理器中电压缩放和软错误率(SER)免疫的电路设计挑战，提出了相关电路技术。通过解决电压-频率缩放带来的低电压操作困难以及逻辑电路对SER的敏感性，实现了在逻辑电路数量增加3倍的情况下保持可靠性和能效。

💡 主要创新点

• 提出了适用于电压缩放的电路设计技术，确保在降低工作电压时逻辑实例的稳定运行。
• 开发了增强SER免疫能力的电路方法，提高处理器对软错误的抵抗力。

🏷 关键词

📄 原文摘要

cores over its predecessor [2], from 2 to 4. It also adds a system interface that is roughly as large as two cores, including six QuickPath interconnects and four FBDIMM channels. This 3× increase in logic circuits per socket presents two major circuit challenges that are addressed in this paper. First, the chip is increasingly dependent on voltage-frequency scaling to fit in an acceptable power envelope. The resulting reduction in typical operating voltage makes it challenging to design the approximately 10 million non-static logic instances; this count excludes the L2 and L3 caches. Key circuit changes and analysis methods that improve low voltage operation are shown. Second, enterprise reliability require that per-socket SER does not increase over the previous processor generation. With

👥 作者与机构

Dan Krueger1, Erin Francom1, Jack Langsdorf2, 1

Intel, Fort Collins, CO Intel, Hudson, MA 2 The 700mm2 65nm Itanium® processor [1] doubles the number of