A Robust 24mW 60GHz Receiver in 90nm Standard CMOS

📋 论文概要

本文在90nm标准CMOS工艺中实现了60GHz接收机前端，功耗仅24mW，且仿真与实测结果高度吻合，解决了毫米波CMOS接收机设计中仿真不准确和量产难度大的问题。

💡 主要创新点

• 首次在90nm标准CMOS中实现60GHz接收机，功耗仅24mW，适合低成本大规模生产。
• 采用鲁棒设计方法，使得仿真结果与实测性能高度匹配，提高了设计的可预测性。

🏷 关键词

📄 原文摘要

Emerging applications for the 60GHz spectrum include extremely high-data-rate short-range communication systems. Many of these applications are expected to enter the realm of consumer electronics where low cost and mass production are prerequisites, favoring the application of digital CMOS technology. In this paper, a highly integrated receiver front-end is demonstrated that is manufactured in a digital CMOS process using a design approach amenable to mass production. Unlike many previous attempts in CMOS, the results of the design are well predicted by the simulation results, matching the desired frequency band and the simulated gain to a very high accuracy. Low noise and high gain are demonstrated with low power consumption. These factors in unison make this front-end suitable for small footprint mobile applications such as a cell phone, PDA, or laptop computer. The design approach relies on carefully modeled building blocks

👥 作者与机构

Bagher Afshar, Yanjie Wang, Ali M. Niknejad

University of California, Berkeley, CA