A 6b 0.2-to-0.9V Highly Digital Flash ADC with Comparator Redundancy

📋 论文概要

该论文提出了一种高度数字化的闪存型ADC架构，能够在0.2V至0.9V的宽电源电压范围内工作，适用于能量受限的微传感器无线网络和植入式生物医学设备。通过引入比较器冗余技术，解决了低电压下器件泄漏和失配问题，实现了低功耗、高能效的模数转换。

💡 主要创新点

• 提出了一种高度数字化的闪存型ADC架构，兼容先进CMOS工艺，支持从亚阈值区（200mV）到近阈值区（900mV）的宽电压工作。
• 采用比较器冗余技术，有效缓解了低电压下器件泄漏和失配对ADC性能的影响，提高了低电压下的转换精度。

🏷 关键词

📄 原文摘要

Microsensor wireless networks and implanted biomedical devices have emerged as exciting new application domains. These applications are highly energy constrained and require flexible, integrated, energy-efficient ADC modules that can ideally operate at the same supply voltage as digital circuits. In many applications, the performance requirements are quite modest (100s kS/s). This paper presents a highly digital ADC architecture compatible with advanced CMOS processes, capable of operating down to a supply voltage of 200mV (i.e., subthreshold regime) and up to 900mV. However, leakage and device variation must be addressed, particularly at low supply voltages. Figure 30.8.1 shows a block diagram of the ADC. The highly digital flash ADC has no bias currents and thus energy is only dissipated through switching events (CV2) and by leakage currents. By minimizing the use of analog circuits, the architecture is compatible with digital CMOS processes. As true differential architectures

👥 作者与机构

Denis C. Daly, Anantha P. Chandrakasan

Massachusetts Institute of Technology, Cambridge, MA