A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration

📋 论文概要

该论文提出了一种用于2-drop DRAM接口的3.2Gb/s 8位单端电流积分DFE接收机，采用内部参考电压生成以减少外部耦合噪声，并通过单环符号-符号LMS算法确定单抽头均衡系数，解决了传统双环实现中的复杂性问题。

💡 主要创新点

• 采用内部参考电压生成技术，减少外部耦合噪声对接收机性能的影响。
• 使用单环符号-符号LMS算法替代传统双环实现，简化了单抽头DFE均衡系数的校准过程。
• 在初始前导码阶段通过发送训练数据完成均衡、参考电压、去偏斜和偏移系数的数字校准。

🏷 关键词

📄 原文摘要

2Gb/s single-ended current-integrating DFE receiver with 8b parallel data for 2-drop DRAM interface is implemented in a 0.18µm CMOS process. The reference voltage for the receiver is generated internally to reduce the external coupling noise. A single-loop implementation of sign-sign LMS algorithm is used to decide the single-tap equalization coefficient of the DFE receiver instead of the previous dual-loop implementation [1]. Equalization, reference voltage, deskew, and offset coefficients are calibrated during the initial preamble-time stage after the power-on reset by sending the training data sequence to the receiver. An open-loop duty-cycle corrector (DCC) is embedded in the PLL loop, to align both rising and falling edges between the PLL input and output

👥 作者与机构

Hyung-Joon Chi1, Jae-Seung Lee1, Seong-Hwan Jeon1,

Seung-Jun Bae2, Jae-Yoon Sim1, Hong-June Park1 1 Pohang University of Science and Technology, Pohang, Korea Samsung Electronics, Hwasung, Korea 2 A 3