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ISSCC 2008Session 23 · NON-VOLATILE MEMORYMemory56nm

A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm

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📋 论文概要

该论文提出了一种采用全位线架构的16Gb MLC NAND闪存,在56nm工艺下实现了34MB/s的编程吞吐量。解决了传统NAND闪存编程速度慢的问题,通过并行编程技术大幅提升了写入性能。

💡 主要创新点

核心指标
34MB/s 编程吞吐量
工艺节点
56nm
重要性
发表年份
ISSCC 2008

🏷 关键词

MLC NAND全位线架构高编程吞吐量56nm工艺

📄 原文摘要

Shouchang Tsao1, Tai-Yuan Tseng1, Khanh Nguyen1, Jason Li1, Jayson Hu1, Jong Park1, Cynthia Hsu1, Fanglin Zhang1, Teruhiko Kamei1, Hiroaki Nasu1, Phil Kliza1, Khin Htoo1, Jeffrey Lutze1, Yingda Dong1, Masaaki Higashitani1, Junhui Yang1, Hung-Szu Lin1, Vamshi Sakhamuri1, Alan Li1, Feng Pan1, Sridhar Yadala1, Subodh Taigor1, Kishan Pradhan1, James Lan1, James Chan1, Takumi Abe2, Yasuyuki Fukuda2, Hideo Mukai2, Koichi Kawakami2, Connie Liang1, Tommy Ip1, Shu-Fen Chang1, Jaggi Lakshmipathi1, Sharon Huynh1, Dimitris Pantelakis1, Mehrdad Mofidi1, Khandker Quader1 1 SanDisk Corporation, Milpitas, CA, 2Toshiba Semiconductor, Yokohama, Japan In the diverse world of NAND flash applications, higher storage capacity is not the only imperative. Increasingly, performance is a differentiating factor and is also a way of creating new markets or expanding existing markets. While conventional memory uses, for

👥 作者与机构

Raul Cernea1, Long Pham1, Farookh Moogat1, Siu Chan1, Binh Le1, Yan Li1,

分类:Memory · 年份:ISSCC 2008