A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed

📋 论文概要

该论文介绍了一种采用45nm自对准接触工艺的1Gb NOR闪存，通过消除相邻字线浮栅之间的耦合，解决了工艺节点缩小带来的单元效应恶化问题，实现了5MB/s的编程速度。

💡 主要创新点

• 采用自对准接触工艺架构，减小了单元尺寸并提高了闪存单元的可靠性。
• 通过消除相邻字线浮栅之间的耦合，防止了单元阈值电压偏移，保持了感测裕度。

🏷 关键词

📄 原文摘要

Robert L. Melcher, Shahnam Khabiri, Nicholas T. Hendrickson, Andrew D. Proescholdt, David A. Ward, Mark A. Taylor Intel, Folsom, CA When transitioning to the 45nm process node, undesirable cell effects become many times worse and it is difficult to meet product requirements while maintaining sense margin in NOR flash. Fig. 23.3.1 shows the self-aligned-contact (SAC) process architecture, which allows cell-size reduction and improves reliability of the flash cells. The SAC architecture eliminates the coupling between floating gates of adjacent wordlines [1]. This prevents cell Vt shift when programming adjacent wordlines and improves margin for MLC sensing. Program performance of 5MB/s requires the development of a number of circuit techniques. These include larger program and verify bandwidth, increased slew rates of high-voltage nodes, maximized throughput of the program microcode, and reduced control

👥 作者与机构

Johnny Javanifard, Tris Tanadi, Hari Giduturi, Kim Loe,