A 9.4-ENOB 1V 3.8µW 100kS/s SAR ADC with TimeDomain Comparator

📋 论文概要

该论文提出了一种采用时域比较器的1V供电、3.8µW功耗、100kS/s采样率的逐次逼近型模数转换器（SAR ADC），实现了9.4位有效位数（ENOB），解决了低功耗传感器系统中高能效模数转换的需求。

💡 主要创新点

• 采用时域比较器替代传统电压比较器，通过时间差检测实现低电压低功耗比较。
• 在亚阈值区操作晶体管，利用恒定功耗与单位增益频率比特性优化能效。
• 整体电路设计实现极低功耗（3.8µW）和优值（FOM）低于0.1pJ/转换步长。

🏷 关键词

📄 原文摘要

The signal bandwidth used in portable or autonomous sensor systems is often lower than 50kHz with ADC requiring about 8 to 10 bits resolution, but the consumed power must be very low: few μW or a FOM = P/(2ENoBfsampl) lower than 0.1pJ/conversion-step. To achieve this target, the successive approximation algorithm is a convenient solution, because it requires only a comparator, a capacitive array and digital logic [1, 2]. In circuits with transistors operated in the sub-threshold region, the ratio between power consumption and unity-gain frequency is almost constant until the leakage current is a negligible fraction of the total. Therefore, it is possible to maintain a low FOM in a reasonably large range of conversion frequencies. However, one additional bit of resolution, when approaching the kT/C noise limit, leads to 4× larger capacitances, with an equivalent increase of power consumption.

👥 作者与机构

Andrea Agnes, Edoardo Bonizzoni, Piero Malcovati, Franco Maloberti

University of Pavia, Pavia, Italy