65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS

📋 论文概要

本文提出一种65nm低功耗高密度SRAM，通过分别控制NMOS和PMOS的体偏置来独立监控阈值电压（Vth），以应对3σ系统变化下的操作裕度问题。该方案有效改善了SRAM在1.0V工作电压下的稳定性，无需使用复杂的辅助电路。

💡 主要创新点

• 采用独立的Vth监控和体偏置机制，分别调整NMOS和PMOS的体偏压，从而精确校正器件阈值电压的不匹配。
• 在65nm工艺下实现1.0V低电压操作，同时保持高密度存储阵列，无需额外辅助电路，降低了设计成本和复杂度。

🏷 关键词

📄 原文摘要

Hitachi, Tokyo, Japan, 2Renesas Technology, Tokyo, Japan Increasing Vth variation is becoming a serious problem in SoCs. Especially in SRAM, Vth variation has a critical impact on operating margins. Self-repairing SRAM [1] uses body bias to improve SRAM operating margin; however, this scheme does not correct the ratio of the Vth values of NMOS and PMOS, which is important for SRAM operation. Assist circuits [2] require special treatment, and also require large design costs. We thus create a body-biased SRAM in which the NMOS and PMOS body biases are separately controlled to maintain the operating margin at the target value by maintaining the ratio between the Vth values of NMOS and PMOS. Furthermore, we design a technique to separately measure the Vth of NMOS and PMOS. This technique is used to determine the body bias of NMOS and PMOS individually. Prototype chips with 1Mb 0.51mm2 high-density SRAM cells using a 65nm low-power process

👥 作者与机构

Masanao Yamaoka1, Noriaki Maeda2, Yasuhisa Shimazaki2, Kenichi Osada1