A 100nm Double-Stacked 500MHz 72Mb SeparateI/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy

📋 论文概要

本文提出一种采用双堆叠S3 SRAM单元的高密度同步SRAM，在100nm工艺下实现72Mb容量和500MHz操作频率。通过自动单元偏置方案和自适应块冗余技术，解决了传统6T SRAM密度不足的问题，同时保持高速访问性能。

💡 主要创新点

• 采用双堆叠单晶硅（S3）SRAM单元，在不牺牲速度的情况下显著提升存储密度
• 提出自动单元偏置方案（Automatic Cell-Bias Scheme），优化工作点并降低漏电流
• 引入自适应块冗余（Adaptive Block Redundancy），提高良率和可靠性

🏷 关键词

📄 原文摘要

Kang-Young Kim, Dae-Gi Bae, Ted Kang, Hoon Lim, Soon-Moon Jung, Hyun-Geun Byun, Young-Hyun Jun, Kinam Kim Samsung Electronics, Hwasung, Korea As multi-core processors become mainstream, the demand for high-density cache memories has increased. Conventional 6T-cellbased SRAMs do not provide enough density for this trend, although they do have the desirable feature of high-speed access. To overcome the density limitation, an SRAM using a doublestacked S3 (stacked single-crystal Si) SRAM cell was introduced for mobile applications [1]. This work demonstrates a high-speed SRAM using double-stacked-cell. From the process point of view, our design uses fully proven technologies for mass production at the sacrifice of cell size, from 25F2 to 36F2 [2]. In addition, peripheral only CoSix layers and a tungsten shunt wordline scheme are used for high-speed operation. From a circuit-design perspective, three schemes are introduced. They are automatic cell

👥 作者与机构

Kyomin Sohn, Young-Ho Suh, Young-Jae Son, Dae-Sik Yim,