A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation

📋 论文概要

该论文提出了一种工作在8-10GHz的低抖动分布式延迟锁定环（DLL），用于生成多相时钟。通过分布式架构解决了传统DLL在高频下因延迟单元失配导致的相位不准确问题。

💡 主要创新点

• 提出分布式DLL架构，适用于8-10GHz高频多相时钟生成。
• 通过分布式设计降低延迟单元失配影响，实现低抖动性能。

🏷 关键词

📄 原文摘要

A conventional DLL employs a phase detector (PD), a charge pump, and a loop filter to compare and adjust the phase difference between the reference clock and the delayed clock. Ideally, when the DLL is locked, the delay of each delay cell is identical and multiple-phase output clocks are generated. However, the random mismatch among the delay cells results in the phase mismatch of the multiple output clocks. Analog or digital calibration techniques [1-4] are applied to resolve the phase inaccuracy. However, implementing a high-frequency DLL by these techniques is challenging because extraneous calibration circuits may increase the intrinsic delay of the delay cell, lower the operating frequency and degrade the jitter performance. Additionally, the jitter performance of the last-phase output clock is always the worst, because the output clock is corrupted by all the noise in its preceding delay cells. To improve the jitter performance and

👥 作者与机构

Keng-Jan Hsiao, Tai-Cheng Lee

National Taiwan University, Taipei, Taiwan