⚡ 本页包含 AI 生成的分析内容，仅供参考
本文介绍了一款采用65nm工艺的第三代16核32线程加32个scout线程的CMT SPARC处理器，通过多核多线程架构和硬件事务内存实现高吞吐量和高单线程性能。
Sun Microsystems, Santa Clara, CA The goals for this high-end commercial microprocessor are high throughput and high single-thread performance, mainframe-class reliability, hardware transactional memory, and linear scalability. We show how these goals are met by the logical and physical design of this 2.3GHz 396mm2 16-core 32-thread plus 32-scout-thread microprocessor. High throughput is achieved by maximizing the number of multithreaded cores that are accommodated with appropriate cache structures on a single 65nm die. In total, 16 small (14mm2) and relatively low-power cores (~10W), supporting a new form of multithreading, deliver 32 threads. Traditional out-of-order execution is discarded due to the large CAMs needed to implement a large instruction window (e.g., 512 rows of over 100b plus recovery structures) and the large re-order buffer necessary to hide current memory latency (500 to 1000 cycles). Another discarded option is a flat
Marc Tremblay, Shailender Chaudhry