A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDR

📋 论文概要

该论文提出了一种40Gb/s CMOS串行链路接收器，集成了自适应均衡器和时钟数据恢复电路，以解决高速数据传输中因趋肤效应和介质损耗引起的严重码间干扰问题。通过消除均衡器与CDR之间的50Ω缓冲器，实现了低功耗和高集成度。

💡 主要创新点

• 提出了一种自适应均衡器架构，能够有效补偿40Gb/s数据速率下的高频损耗。
• 将均衡器与CDR电路单片集成，省去了片间50Ω缓冲器，降低了功耗和面积。

🏷 关键词

📄 原文摘要

Modern broadband communication systems require high-speed receivers to process serial data at tens of gigabits per second. As the data rate reaches 40Gb/s, skin-effect and dielectric loss in the transmission medium cause significant loss at high frequencies, leading to considerable ISI even if the data is transmitted over a short copper cable. To reduce the ISI and improve the BER, extensive equalization is required in the receiver side. It is also highly desirable to integrate the equalizer with the CDR circuit on the same chip, which eliminates the 50Ω buffer between the two circuits and saves the overall power consumption. Though a 40Gb/s equalizer has been verified in 0.18μm CMOS using distributed tap amplifiers [1], in addition to the non-distributive CMOS equalizers at 10 to 20Gb/s [2, 3], the speed of equalizer/CDR combination has remained below 10Gb/s [4, 5]. This paper describes a 40Gb/s CMOS serial-link receiver that

👥 作者与机构

Chih-Fan Liao, Shen-Iuan Liu

National Taiwan University, Taipei, Taiwan