⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文设计了一款采用50nm工艺的8Gb NAND闪存，通过优化编程电路和DDR接口，实现了100MB/s的编程吞吐量和200MB/s的数据传输速率，满足了SSD、混合硬盘和游戏机等应用对高性能读写的要求。
June Lee1, Erwin Yu1, Allahyar Vahidimowlavi1, Michael Abraham1, Sanjay Talreja2, Rajesh Sundaram2, Rod Rozman2, Luyen Vu1, Chih Liang Chen1, Uday Chandrasekhar1, Rupinder Bains2, Vimon Viajedor1, William Mak1, Munseork Choi1, Darshak Udeshi2, Michelle Luo1, Shahid Qureshi1, Jeffrey Tsai1, Frederick Jaffin1, Yujiang Liu1, Marco Mancinelli1 1 Micron, San Jose, CA Intel, Folsom, CA 2 NAND flash has been steadily growing in popularity among different applications such as SSD, hybrid HDD, and game consoles; and new applications are emerging that require higher read/write performance. A 3.3V 8Gb NAND Flash memory with a synchronous double-data-rate (DDR) interface is designed and fabricated using 3M 50nm technology to meet the requirements of these markets. We achieve a NAND Flash program throughput of 100MB/s with quad-plane operation, which is 5× previously reported [1,2]. I/O read/write throughput of 200MB/s is achieved using a newly
Dean Nobunaga1, Ebrahim Abedifard1, Frankie Roohparvar1,