A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques benefits of FBB and RBB (Fig. 13.2.3). This ABB approach achieves an optimal balance of performance and power with circuit techniques alone, eliminating the need for additional LVT or HVT logic transistors.

📋 论文概要

本文提出一款采用45nm工艺的3.5G基带与多媒体应用处理器，通过自适应体偏置和超低功耗技术降低功耗。通过分离存储阵列与外围逻辑电源，有效减少了SRAM和ROM外围泄漏电流，从而降低SoC有源功率。

💡 主要创新点

• 采用自适应体偏置技术动态调整阈值电压，平衡性能与泄漏功耗。
• 将存储外围电源与阵列电源分离，外围逻辑使用核心电压以降低泄漏功率。
• 集成250个SRAM/ROM实例，通过整体泄漏管理优化SoC功耗。

🏷 关键词

📄 原文摘要

Robert Pitts, Fabien Jumel, Stacey Engel, Philippe Royannez, Rolf Lagerquist, Hugh Mair, Jeff Vaccani, Greg Baldwin, Keerthi Heragu, Rituparna Mandal, Michael Clinton, Don Arden, Uming Ko The device has 16Mb of SRAM and ROM in ~250 instances, making leakage reduction in both the memory arrays and the memory periphery logic critical to overall SoC active power. Periphery leakage power reduction is accomplished by separating the periphery power supply from array power supply. In this way, the core logic voltage is applied to the non-bit cell portion of the memory thus reducing power while the array power is controlled separately to ensure bit stability [2]. Additionally, segmenting the memory array into multiple blocks allows for array leakage reduction (Fig. 13.2.4). Individual blocks are put into a low leakage power state, providing a 2× leakage reduction when that block is not being accessed.

👥 作者与机构

Gordon Gammie, Alice Wang, Minh Chau, Sumanth Gururajarao,