A 320mV 56µW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS

📋 论文概要

该论文提出了一款在65nm CMOS工艺中实现的超低电压运动估计加速器，能够在230mV至1.4V的宽电压范围内工作，以优化能量-延迟权衡。它专门用于实时视频编码中的绝对差值和（SAD）计算，在320mV电压下仅消耗56µW功率，实现了411 GOPS/Watt的能效。

💡 主要创新点

• 采用超低电压（低至230mV）工作模式，大幅降低功耗，同时通过宽电压范围支持动态能量-延迟优化。
• 针对运动估计中的SAD计算进行专用硬件加速，在极低功耗下实现高能效（411 GOPS/Watt）。

🏷 关键词

📄 原文摘要

the most performance and power-critical operation in video encoding applications, where a wide range of throughput and power constraints are required to handle a variety of video resolution, frame rate and application specifications [1,2]. A motion estimation engine targeted for special-purpose on-die acceleration of sum of absolute difference (SAD) computation in real-time video encoding workloads on power-constrained mobile microprocessors is fabricated in 65nm CMOS [3]. The accelerator operates over a wide range of supply voltages (1.4V to 230mV) to enable optimal energy-delay trade-off by dynamically varying operating conditions based on target performance demands and power budgets. Total power consumption for SAD of 8 pixel pairs is 56μW, resulting in a peak energy efficiency of

👥 作者与机构

Himanshu Kaul, Mark Anders, Sanu Mathew, Steven Hsu,

Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar Intel, Hillsboro, OR Motion estimation for compressing inter-frame redundancies is