A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency

📋 论文概要

该论文提出了一种对工艺变化容忍的浮点运算单元，通过电压插值和可变延迟技术来应对工艺变化对关键路径延迟的影响，从而提升处理器在变化条件下的性能和能效。

💡 主要创新点

• 提出电压插值技术，动态调整电压以补偿工艺变化引起的延迟变化。
• 引入可变延迟架构，允许关键路径根据实际延迟动态调整，避免固定频率限制。

🏷 关键词

📄 原文摘要

Process variation will greatly impact the power and performance of future microprocessors. Design approaches based on multiple supply or threshold voltage assignment provide techniques to statically tune critical path delays for energy savings [1]. However, under process variation, the delay of critical paths may vary, and a large number of critical paths in circuits reduces the maximum operating frequency of pipelined processors. One proposed postfabrication solution is to adaptively tune the back-body bias to combat variations for logic structures [2]. Dynamic voltage switching between two power supplies, using level shifters to cross voltage domains, has also been proposed to primarily reduce power [35]. This paper explores two fine-grained, post-fabrication circuittuning techniques to combat process variation for pipelined logic components—voltage interpolation and variable latency. These

👥 作者与机构

Xiaoyao Liang, David Brooks, Gu-Yeon Wei

Harvard University, Cambridge, MA