⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文设计了一个24GHz次谐波接收机前端，集成了多相本振生成电路，采用65nm CMOS工艺实现。解决了Ka波段和毫米波接收机中低功耗、高集成度与鲁棒性的权衡问题。
in the design of Ka band and mm-wave silicon ICs has motivated several industrial projects toward the realization of chipsets for broadband communications and automotive cruise control applications. Performance of standard CMOS implementations has proved sufficient up to 60GHz range and examples of operating blocks even beyond 60GHz have been presented [1, 2]. Still, the choice of the receiver architecture entails several peculiar considerations in order to achieve a robust low-power solution. Frequency conversion to DC or close to DC has been used in most cases to allow a high level of integration in CMOS. On the other hand, at high frequencies, to save power in both the VCO and dividers, it is desirable to synthesize a reference
Andrea Mazzanti1, Marco Sosio2, Matteo Repossi3, Francesco Svelto2, 1
University of Modena and Reggio Emilia, Modena, Italy University of Pavia, Pavia, Italy, 3STMicroelectronics, Pavia, Italy 2 The outcome of the recent research effort