A 1.9µW 4.4fJ/Conversion-step Charge-Redistribution ADC 10b 1MS/s

📋 论文概要

该论文提出了一种用于能量采集系统的低功耗10位1MS/s逐次逼近型ADC，采用电荷再分配DAC、动态两级比较器和延迟线控制器，实现了无静态偏置电流且功耗与采样率成正比。其功耗仅为1.9µW，品质因数达4.4fJ/conversion-step。

💡 主要创新点

• 采用电荷再分配DAC代替传统电阻串DAC，消除了静态偏置电流，使功耗与采样率线性相关。
• 设计了一种动态两级比较器，仅在比较阶段消耗动态功耗，进一步降低整体功耗。
• 引入基于延迟线的异步控制器，省去外部高频时钟，简化系统并降低功耗。

🏷 关键词

📄 原文摘要

Future systems powered by energy scavenging, e.g., wireless sensor nodes, demand μW-range ADCs with no static bias currents in order to have a power dissipation proportional to the sample rate. An ADC that meets these requirements by using a charge-redistribution DAC, a dynamic 2-stage comparator, and a delay-line-based controller is realized in CMOS. Figure 12.4.1 shows a DAC based on charge redistribution, with a binary-weighted capacitor array [1]. The left side of every capacitor can be switched between a low reference voltage, Vref-, and a high reference voltage, Vref+, using a simple digital inverter. If the left side of capacitor CMSB is switched from low to high, the step on output VDAC is ΔVDAC = (Vref+ - Vref-)*CMSB/Ctot, where Ctot is the total

👥 作者与机构

Michiel van Elzakker1,2, Ed van Tuijl1,3, Paul Geraedts1,

Daniel Schinkel1,3, Eric Klumperink1, Bram Nauta1 1 University of Twente, Enschede, Netherlands Philips Research, Eindhoven, Netherlands 3 Axiom IC, Enschede, Netherlands 2