← 返回论文列表 📄 下载原文 PDF  ISSCC 2008 · 25.6
ISSCC 2008Session 25 · BUILDING BLOCKS FOR HIGH-SPEED TRANSCEIVERSWireline I/O90nm CMOS

A 1.8W 115Gb/s Serial Link for Fully Buffered DIMM with 2.1ns Pass-Through Latency in 90nm CMOS

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

该论文提出了一种用于全缓冲DIMM(FBDIMM)的串行链路,以115Gb/s的总数据率实现2.1ns的超低穿透延迟,功耗仅1.8W。通过采用90nm CMOS工艺,解决了传统并行分支总线限制内存带宽和容量的问题。

💡 主要创新点

核心指标
115Gb/s, 1.8W, 2.1ns pass-through latency
工艺节点
90nm CMOS
重要性
发表年份
ISSCC 2008

🏷 关键词

串行链路全缓冲DIMM低延迟高带宽

📄 原文摘要

Carlos Carvalho, Reza Yousefi, Muhammad Ali Khan, Trevor Monson, Mark Ayoub, Claus Reitlingshoefer Diablo Technologies, Gatineau, Canada Bandwidth and capacity of memory systems based on commodity DIMM are limited by the parallel stub bus between the modules and the memory controller. As a result, the maximum number of DIMMs per channel has to be reduced with the market entrance of every new DRAM generation. Fully buffered DIMMs (FBDIMM) eliminate this limitation by replacing the parallel stub bus by a serial point-to-point link with a repeater device (advanced memory buffer (AMB)) residing on every FBDIMM. While solving the bandwidth-capacity problem, FBDIMM systems potentially increase the memory latency. Keeping the pass-through latency below 3ns, combined with careful command sequencing [1], alleviates the latency problem. Another challenge associated with FBDIMM is the high power consumption of the AMB. Current

👥 作者与机构

Dirk Pfaff, Sivakumar Kanesapillai, Volodymyr Yavorskyy,

分类:Wireline I/O · 年份:ISSCC 2008