A 94GHz Locking Hysteresis-Assisted and Tunable CML Static Divider in 65nm SOI CMOS

📋 论文概要

该论文提出了一种在65nm SOI CMOS工艺中实现的94GHz锁定迟滞辅助可调CML静态分频器，解决了毫米波分频器在高频和宽频率范围性能上的不确定性。通过引入锁定迟滞辅助和可调技术，实现了高频分频和低功耗性能。

💡 主要创新点

• 提出锁定迟滞辅助技术，增强了分频器在高频下的锁定稳定性。
• 采用可调CML静态分频器结构，实现了宽频率范围的分频操作。
• 在65nm SOI CMOS工艺中实现了94GHz的分频频率，展示了CMOS技术在毫米波频段的潜力。

🏷 关键词

📄 原文摘要

As an essential clock-system component, millimeter-wave dividers have been implemented for V- and W-band channels [1-8]. This has also served as a standard benchmark vehicle that reveals highspeed and low-power performances of a technology. Through technology scaling, CMOS CML static divider high-frequency performances have been scaled [6-8], and they are comparable to dividers in other technologies [1-5]. In addition to the device performance, circuit design and measurement determine the divider high-speed and wide frequency range performance. One of the uncertainties in CML static divider measurement is pulling and locking hysteresis. By using CML static divider topology, the divider has been assumed to have a fixed wide operation range, from DC to the fdiv,max, the maximum input-referred divider operational frequency. In fact, the CML static dividers show a certain degree of locking hysteresis, similar to

👥 作者与机构

Daeik D. Kim, Jonghae Kim, Choongyeun Cho

IBM, Hopewell Junction, NY