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本文提出一种在90nm CMOS工艺下实现的300MS/s 8位子区式ADC，通过采用分裂负载插值放大器（SLA）阵列，将并行预放大器和比较器数量减半，从而将面积和功耗降低一半，解决了传统子区式ADC中大量并行连接造成的瓶颈问题。
Subranging ADCs meet these requirements by using simple open-loop amplifiers [1, 2]. However, the large number of parallel connected differential amplifiers (pre-amps) and comparators create a bottleneck, making it difficult to decrease area and power consumption in this type of ADC. This paper presents circuit techniques capable of halving area and power requirements by reducing the number of parallel-connected pre-amps and comparators by half, compared with conventional subranging ADC design techniques. A split-load interpolation amplifier (SLA) operates as the pre-amp, which allows the ADC to perform Nb quantization with the same area and power consumption used to perform (N-1)b quantization. The 300MS/s 8b ADC is based on a 2-step subranging architecture and composed of a 4b coarse parallel ADC (CADC)
Yasuhide Shimizu, Shigemitsu Murayama, Kohhei Kudoh, Hiroaki Yatsuda
Sony LSI Design, Nagasaki, Japan Fast, area- and power-efficient ADCs are required for mixed-signal SoCs