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本文提出一种采用三电平(+1, 0, -1)电流导引单元架构的过采样音频DAC,通过动态元素匹配(DEM)技术实现108dB SNR和1.1mW的低功耗性能。相比传统两电平单元,三电平架构在零状态时断开单元,消除其热噪声贡献,降低了功耗并提高了信噪比。
use 2-level (+1, -1) unit elements in either switched-capacitor or current-steering form. This paper presents a low-power audio DAC that uses a 3-level current-steering unit element architecture. When compared to the 2-level unit element architecture, the 3level (+1, 0, -1) unit element DAC architecture has several significant advantages that make it preferable for a low-power design. First, when an input data bit is in the “zero” (or OFF) state, the corresponding current-steering element is disconnected from the DAC output and does not contribute any thermal noise to the output. Thus, the current density of each element can be significantly reduced. Second, at low-level input signal (-60dB full-scale and below) condition, the activity of the unit elements is much less
Khiem Nguyen, Abhishek Bandyopadhyay, Bob Adams,
Karl Sweetland, Paul Baginski Analog Devices,Wilmington, MA Previously reported multi-bit oversampling ΔΣ audio DACs [1, 2]