A Resonant Global Clock Distribution for the Cell Broadband-EngineTM Processor

📋 论文概要

该论文提出了一种用于Cell宽带引擎处理器的谐振全局时钟分配技术，通过集成电感器和边缘电容器来降低时钟功耗并改善时钟抖动。解决了高性能处理器中全局时钟分布的高功耗和时序稳定性问题。

💡 主要创新点

• 创新点1：采用谐振时钟技术替代传统时钟树，利用LC谐振减少全局时钟的功耗和抖动。
• 创新点2：在芯片最后金属层设计小型电感器，避开C4焊盘阵列，实现紧凑布局。
• 创新点3：引入边缘电容器使时钟波形正确居中于电源轨之间，均衡电压纹波和启动时间。

🏷 关键词

📄 原文摘要

Junction, VT which results in a good balance between voltage ripple (affects power savings and skew/jitter improvement) and time to reach steady state (affects startup and low-frequency operation). The purpose of the fringe capacitor is to allow the clock waveform to be correctly centered between the supply rails [2]. Figure 28.4.7 is a die micrograph of a small section of the chip showing the columns of inductors and C4 pads on the last metal level. The inductors are small enough to avoid the C4 pad array. 2 Resonant clocking techniques [1,2] show promise in reducing global clock power and timing uncertainty (skew and jitter). By resonating the large global clock capacitance with an inductance, the energy used to charge the clock node each period can be recycled

👥 作者与机构

Steven Chan1, Phillip Restle1, Thomas Bucelot1, Stephen Weitzel2,

John Keaty2, John Liberty2, Brian Flachs2, Richard Volant3, Peter Kapusta4, Jeff Zimmerman4 1 IBM, Yorktown Heights, NY IBM, Austin, TX 3 IBM, Hopewell Junction, NY 4 IBM, Essex